Japanese patent application No. 11-233965, filed Aug. 20, 1999, is hereby incorporated by reference in its entirety.
The present invention relates to semiconductor devices having a non-volatile memory transistor and includes a semiconductor device comprising a non-volatile memory transistor with a split gate structure.
There are a variety of different types of non-volatile memory transistors. One type of the non-volatile memory transistors can electrically write and ease data. Such type also runs a great variety. For example, one of the non-volatile memory transistors has a P-type semiconductor substrate, a P-type well located in the semiconductor substrate, a source and drain of an N-type located in the well and a gate with a split-gate structure located over the well through a thin insulation layer.
In a non-volatile memory transistor having the above-described structure, the semiconductor substrate is normally grounded, and therefore the well has a ground potential. As a result, a high voltage of one polarity (for example, a positive polarity) must be used for data writing and erasing operations.
One embodiment relates to a semiconductor device having a non-volatile memory transistor having a split structure. The semiconductor device includes a semiconductor substrate of a first conductivity type having a memory region. A first well of a second conductivity type is located in the memory region, and a second well of a first conductivity type located in the first well. The non-volatile memory transistor includes a source and drain that are located in the second well. In one aspect of certain embodiments, the semiconductor substrate is a p-type, the first well is an n-type, the second well is a p-type, and each of the pair of source and drain is an n-type.
Other embodiments relate to a semiconductor device having a non-volatile memory transistor having a split-gate structure, the semiconductor device including a semiconductor substrate of a first conductivity type having a memory region. The semiconductor device also includes a first well of a second conductivity type located in the memory region and a second well of a first conductivity type located in the first well. The non-volatile memory transistor includes a source and drain that are located in the second well. The non-volatile memory transistor includes a split gate structure including a source, a drain, a gate insulation layer, a floating gate, an intermediate insulation layer adapted to act as a tunnel insulation layer, and a control gate. The intermediate insulation layer is composed of at least three insulation layers, wherein a first layer of the three insulation layers contacts the floating gate, a third layer contacts the control gate, and a second layer is located between the first and third layers.
Other embodiments relate to a semiconductor device having a non-volatile memory transistor having a split-gate structure. The semiconductor device includes means for performing an data writing operation using a first voltage of a first polarity and a data erasing operation using a second voltage of a second polarity opposite from that of the first polarity. The means include a substrate selected from the group of a P-type substrate and an N-type substrate, a first well of an opposite type than the substrate, a second well of an opposite type than the first well, and a source and drain formed in the second well.